As is known, during certain processes performed in a router or other type of packet switch of a packet processing system, packets may be segmented into subsets or portions of data referred to as “cells.” For example, packets may be segmented into cells during router framing operations. However, these cells of data must be reassembled back into packets or protocol data units (PDUs) for use by other processes or functions performed in the router.
Conventional routers typically reassemble packets and store them in a common reassembly memory for subsequent use by multiple functions performed by the router. Such functions may include, for example, packet classification and packet scheduling. However, as is known, reassembling packets for use by such multiple functions requires very high input and output bandwidth.
The use of a common, high bandwidth memory to perform multiple functions has many significant drawbacks. First, such a high bandwidth memory can be quite expensive. It also typically causes any associated memory interface device to be expensive too because of requirements such as extra pins, special buffers and special control mechanisms. Further, the use of a common, high bandwidth reassembly memory makes the memory partitioning design task very difficult, particularly if the design is implemented in multiple integrated circuits.
It is therefore apparent that a need exists for techniques which address these and other drawbacks associated with the use of a common, high bandwidth memory for storing reassembled packets for subsequent use in multiple functions performed in a packet processing system.